With development of semiconductor technologies, integrated circuits (ICs) move toward large scales. However, large scale integration (LSI) faces challenges including how to improve integration density of semiconductor devices and also how to reduce power consumption. It is therefore desirable for transistors, as one of the most basic semiconductor devices in ICs, to reduce their turn-on voltage and to reduce power consumption of the ICs.
FIG. 1 schematically depicts a cross-sectional view of a conventional transistor. As shown in FIG. 1, the transistor includes: a semiconductor substrate 100; a gate dielectric layer 101 made of silicon oxide and formed on the semiconductor substrate 100; a gate electrode layer 102 made of polycrystalline silicon and formed on the gate dielectric layer 101; a sidewall spacer 103 made of silicon oxide and/or silicon nitride and formed on both sides of the gate dielectric layer 101 and the gate electrode layer 102; and source/drain regions 104 formed within the semiconductor substrate 100 on both sides of the sidewall spacer 103 and the gate electrode layer 102. When the transistor is a PMOS transistor, the semiconductor substrate 100 can be doped to form an n-well therein prior to forming the gate dielectric layer 101, and the source/drain regions 104 can be implanted with p-type ions. When the transistor is an NMOS transistor, the semiconductor substrate 100 can be doped to form a p-well therein prior to forming the gate dielectric layer 101, and the source/drain regions 104 can be implanted with n-type ions.
Existing transistors require a high turn-on voltage, which in turn requires the transistors to be maintained at a high working voltage. Consequently, the ICs containing these transistors have high power consumption.
Thus, there is a need to provide a transistor with a reduced turn-on voltage and reduced power consumption, and a method of making the transistor.